1. Field of the Invention
The present invention relates to a semiconductor memory device having twin wells and a manufacturing method thereof.
2. Description of Related Art
There are a variety of different types of SRAMs, one form of semiconductor memory devices. One type of SRAMs employs CMOS devices. SRAMs using the CMOS have been aggressively developed in recent years since the CMOS has excellent characteristics such as low power consumption. However, the CMOS has a serious drawback in that it exhibits a latch-up phenomenon.
It is an object of the present invention to solve the problems as described above. It is another object of the present invention to provide a semiconductor memory device having a construction in which the latch-up phenomenon hardly occurs, and a method for manufacturing the same.
In accordance with one embodiment of the present invention, a semiconductor memory device has a semiconductor substrate, a peripheral circuit region and a memory cell region on the principal surface of the semiconductor substrate. The semiconductor memory device has a first well formed in the peripheral circuit region, a first conductivity type second well formed in the memory cell region, a second conductivity type third well formed in the memory cell region and having substantially the same depth as the depth of the second well, and a device element isolator formed in the memory cell region for isolating the device element formed in the second well from the device element formed in the third well. The second and third wells extend to an area under the device element isolator. The second and third wells may be further provided with a first layer having a depth shallower than the first well, and a second layer having the same depth as the first well. The first layer of the second well overlaps the first layer of the third well under the device element isolator. The second layer of the second well and the second layer of the third well are isolated from each other.
The depth of the first layer in the second and third wells formed in the memory cell region may be shallower than the depth of the first well formed in the peripheral circuit region in accordance with one embodiment of the present invention. Accordingly, overlap of the first layers at the boundary between the first layer in the second well and the first layer in the third well under the device element isolator can be diminished. The reasons will be described below. Therefore, in accordance with an embodiment of the present invention, the distance between one well and a source/drain in another well formed adjacent to the one well may be prevented from becoming too short without elongating the length of the device element isolator. Consequently, the embodiment structure prevents an increase in the leak current in a parasitic MOS that triggers the latch-up phenomenon while miniaturizing the semiconductor memory device.
In accordance with one embodiment, the second and third wells may have second layers. Resistance of the second and third wells (substrate resistance) can be lowered by the second layers, while preventing occurrence of the latch-up phenomenon.
In accordance with one embodiment, the second layer in the second well and the second layer in the third well are isolated from each other. If the two layers were to have contact with each other, the overlap between the second well and the third well at their boundary could not be reduced. The reason will also be described below.
In accordance with embodiments of the present invention, the device element isolator includes a LOCOS oxide film, a semi-recess LOCOS oxide film, and a shallow trench (with a depth of about 0.4 to 0.8 xcexcm) or the like. The term xe2x80x9csource/drainxe2x80x9d refers to at least one of a source region and a drain region.
The second well has the same depth as the depth of the third well in accordance with one embodiment of the present invention. Therefore, substantially no imbalance in performance between transistors, attributable to the difference between the well depths, occurs in the memory cell region. It is noted that, in this specification, the term xe2x80x9cthe same depthxe2x80x9d is not strictly limited to the same depth but also covers a well depth difference that causes substantially no imbalance in performance between transistors.
Since the second well has the same depth as the third well according to the present invention, the depth of the source/drain in the second well can be adjusted to be the same as the depth of the source/drain in the third well. Therefore, no imbalance in performance among transistors due to different depths of the source/drain is caused.
In accordance with one embodiment of the present invention, the source/drain to be formed in the second and third wells does not become too shallow, compared to the source/drain to be formed in the first well.
The well contact region for fixing the well potential is isolated from the source/drain. The second and third wells extend to a position under the device element isolator. Consequently, the wells can be extended to the well contact region, allowing the second and third wells to be readily connected to the well contact region.
The source/drain of a transistor formed in the first well, the source/drain of a transistor formed in the second well and the source/drain of a transistor formed in the third well preferably have substantially the same depth in accordance with one embodiment of the present invention. As a result, sources/drains of the same conductivity type can be simultaneously formed.
In a preferred embodiment of the present invention, the first, second and third wells are retrograded wells. The retrograded well refers to a well formed by high-energy ion implantation without using a thermal diffusion method.
Each of the first, second and third well as a retrograded well is provided with a layer with a first concentration, a layer with a second concentration, a layer with a third concentration and a layer with a fourth concentration in the order from the top to the bottom. The first layer in the second well and the first layer in the third well are composed of the layers with the first, second and third concentrations. The second layer in the second well and the second layer in the third well are composed of the layers with the fourth concentration. The layer with the first concentration comprises, for example, a channel doped layer for adjusting the threshold voltage Vth of the transistor. The layer with the second concentration comprises, for example, a punch-through stopper layer for suppressing a short-channel effect of the transistor. The layer with the third concentration comprises, for example, a channel-cut layer for preventing action of a parasitic transistor in a region including the device element isolator. The layer with the fourth concentration comprises, for example, a low resistive layer for decreasing the well resistance.
In accordance with one embodiment of the present invention, a CMOS type cell SRAM is formed in the memory cell region. The CMOS type cell SRAM refers to an SRAM in which the cell is composed of the CMOS.
In a preferred embodiment of the present invention, the length of the device element isolator for dividing adjacent wells in the memory cell region is in the range of about 0.2 xcexcm to 1.6 xcexcm. Since the boundary between the second well and the third well is required to be located under the device element isolator, and a positional deviation may occur in patterning the resist, a minimum length to cover the positional deviation is necessary in the device element isolator. This minimum length may preferably be about 0.2 xcexcm. When the length of the device element isolator is longer than 1.6 xcexcm, the memory cell size may become too large.
The depth of the first layers in the second and third wells is preferably in the range of about 0.5 xcexcm to 1.2 xcexcm in accordance with one embodiment of the present invention. When the depth of the first layer in the second and third wells is less than about 0.5 xcexcm, the depth of the device element isolator may become deeper than the depth of the first layer, thereby causing a problem in forming the well contact region for fixing the well potential. When the depth of the first layers in the second and third wells is deeper than about 1.2 xcexcm, an overlap between the first layer in the second well and the first layer in the third well at the boundary under the device element isolator may become too large.
In a preferred embodiment of the present invention, the first well comprises a first conductivity type well and a second conductivity type well. In other words, the first well comprises a twin well.
By the construction described above, the first conductivity type well in the first well and the second well can be simultaneously formed, and the second conductivity type well in the first well and the third well can be simultaneously formed.
In accordance with another embodiment of the present invention, a semiconductor memory device has a semiconductor substrate defining a peripheral circuit region and memory cell region on the principal face, a first well formed in the peripheral circuit region, a first conductivity type second well formed in the memory cell region, and a second conductivity type third well formed in the memory cell region, the second and third wells having a first layer and a second layer extending to a position under the first layer, and the second well and the third well having the same depth with each other. The semiconductor memory device may be formed by the following steps: (a) a device element isolator is formed on the principal surface; (b) a resist pattern is formed on the principal surface, in which an opening in the resist pattern is positioned at the second well forming region so that the second layer in the second well does not make contact with the third well; (c) the second layer is formed in the second well at the position under the device element isolator by ion-implantation of impurities in the second well forming region; (d) a resist pattern is formed on the principal surface, in which an opening in the resist pattern is positioned at the third well forming region so that the second layer in the third well does not make a contact with the second well; (e) the second layer of the third well is formed at the position under the device element isolator by ion-implantation of impurities in the third well forming region; (f) a resist pattern is formed on the principal surface, in which an opening in the resist pattern is positioned at the second well forming region; (g) the first layer is formed in the second well at a position under the device element isolator by ion-implantation of impurities in the second well forming region; (h) a resist pattern is formed on the principal surface, in which an opening of the resist pattern is positioned at the third well forming region; and (i) the first layer is formed in the third well at a position under the device element isolator by ion-implantation of impurities in the third well forming region.
In accordance with embodiments of the present invention, a semiconductor memory device can be manufactured in such a manner that the distance between a well and a source/drain formed in another well adjacent to the well does not become too short without having to undesirably extend the length of the device element isolator, and the resistance of the second and third wells is lowered.
In a preferred embodiment of the present invention, a resist pattern having a thickness of about 3.0 xcexcm to 8.0 xcexcm is used as a mask in step (b) and step (d), and a resist pattern having a thickness of about 1.2 xcexcm to 2.5 xcexcm is used as a mask in step (f) and step (h).
When the thickness of the resist pattern in steps (b) and (d) is smaller than about 3.0 xcexcm, impurities may pass through the resist pattern during ion-implantation for forming the retrograded well. When the thickness of the resist pattern is larger than about 8.0 xcexcm, on the other hand, the shape of the end of the resist pattern is hardly controllable, causing a problem that the length of the device element isolator becomes elongated.
When the thickness of the resist pattern in steps (f) and (h) is smaller than about 1.2 xcexcm, impurities may shoot through the resist pattern during ion-implantation for forming the retrograded well. When the thickness of the resist pattern is larger than about 2.5 xcexcm, on the other hand, the dimensional accuracy of the resist becomes poor, causing a problem that overlap between the second well and third well under the device element isolator becomes large.
Either a positive resist or a negative resist can be used in steps (b) and (d). Also, a positive resist or a negative resist can be used in steps (f) and (h). However, preferably, a positive resist may be used in steps (f) and (h), because the positive resist is excellent in controlling the verticality and dimensions of edges of the resist pattern.
Preferably, side faces of the openings formed in the resist patterns in steps (b) and (d) may be deviated toward an active region side by about 0.3 xcexcm to 0.8 xcexcm from the center of the device element isolator.
The resist pattern suffers a light proximity effect, loading effect and alignment error. The second layer in the well overlaps the first layer in the confronting well when the deviation is smaller than 0.3 xcexcm.
On the other hand, when the deviation is larger than about 0.8 xcexcm, the dimension of the opening of the resist pattern becomes too small. As a result, accuracy in matching the resist patterns deteriorates substantially.
Other features and advantages of the invention will be apparent from the following detailed description, taken in conjunction with the accompanying drawings which illustrate, by way of example, various features of embodiments of the invention.